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 HD74LS75
Quadruple Bistable Latches
REJ03D0416-0300 Rev.3.00 May 10, 2006 The HD74LS75 is ideally suited for use as temporary storage for binary information between processing units and input / output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable (G) is high and the Q output will follow the data input as long as the enable remains high. When the enable goes low, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go high. This device features complementary Q and Q outputs from a 4-bit latch.
Features
* Ordering Information
Part Name HD74LS75P HD74LS75FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
1Q 1D 2D Enable 3-4 VCC 3D 4D 4Q
1 Q 2 3 4 5 6 7 8 Q Q Q G G G G Q D D Q Q D D Q
16 15 14 13 12 11 10 9
1Q 2Q 2Q Enable 1-2 GND 3Q 3Q 4Q
(Top view)
Rev.3.00, May 10, 2006, page 1 of 5
HD74LS75
Function Table
Inputs D L H X G H H L Q L H Q0 Outputs Q H L Q0
H; high level, L; low level, X; irrelevant Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q0 before the indicated steady-state input conditions were established.
Circuit Schematic (1/4)
Data To Other Latch Enable Q Q
Absolute Maximum Ratings
Item Symbol Ratings Supply voltage VCC 7 Input voltage VIN 7 Power dissipation PT 400 Storage temperature Tstg -65 to +150 Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Unit V V mW C
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Pulse width Setup time Hold time Symbol VCC IOH IOL Topr tw tsu th Min 4.75 -- -- -20 20 15 5 Typ 5.00 -- -- 25 -- -- -- Max 5.25 -400 8 75 -- -- -- Unit V A mA C ns ns ns
Rev.3.00, May 10, 2006, page 2 of 5
HD74LS75
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL D input G input D input G input D input G input IIH IIL II min. 2.0 -- 2.7 -- -- -- -- -- -- -- -- typ.* -- -- -- -- -- -- -- -- -- -- -- max. -- 0.8 -- 0.4 0.5 20 80 -0.4 -1.6 0.1 0.4 Unit V V V V A mA mA Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Input current
Short-circuit output -20 -- -100 mA IOS current Supply current** ICC -- 6.3 12 mA Input clamp voltage VIK -- -- -1.5 V Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with all outputs open and all inputs grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Inputs D D G G Outputs Q Q Q Q min. -- -- -- -- -- -- -- -- typ. 15 9 12 7 15 14 16 7 max. 27 17 20 15 27 25 30 15 Unit ns ns ns ns Condition
Propagation delay time
CL = 15 pF, RL = 2 k
Rev.3.00, May 10, 2006, page 3 of 5
HD74LS75
Testing Method
Test Circuit
VCC DG QQ
RL P.G. Zout = 50 D Q Q
RL
G P.G. Zout = 50
CL
CL
Notes:
1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H).
Waveform
tTLH 90% 1.3 V 10% tsu tTLH 90% 90% 1.3 V 1.3 V 10% 10% 500ns tPLH Q 1.3 V tPLH tPLH 1.3 V tPHL tPHL 1.3 V VOL VOH 1.3 V VOL tPLH 500ns tPHL VOH th tTHL 1s 90% 1.3 V 10% tsu th 3V 1.3 V 1.3 V 0V tPHL tTHL 1s 3V 1.3 V 0V
D
G
Q
Notes:
1. Input pulse; D input: PRR = 500 kHz, G input; PRR = 1 MHz, tTHL 10 ns,tTLH 10 ns. 2. When measuring propugation delay times from the D input, the corresponding G input must be held high.
Rev.3.00, May 10, 2006, page 4 of 5
HD74LS75
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Dimension in Millimeters Symbol
c
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50
0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
Rev.3.00, May 10, 2006, page 5 of 5
A
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Colophon .6.0


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